Interrupts

Tech 19 Sep 2026 5 min read

NIC Interrupt Moderation Trades Wakeup Rate for Packet Latency

A network adapter does not need to interrupt a CPU for every received packet or completed transmission. Many NICs can hold interrupt delivery briefly and report several completion events together. This interrupt moderation reduces interrupt traffic and CPU entry overhead, but it can also delay the moment software notices newly completed work. The mechanism sits between packet DMA and the driver’s receive or transmit processing. It changes notification timing; it does not change the packet’s wire format, Ethernet ordering rules, or the basic requirement that the driver eventually process completed descriptors.

Networking Linux

Tech 19 Sep 2026 7 min read

MSI-X Per-Vector Masking Separates Interrupt Control Across Device Queues

MSI-X Per-Vector Masking Separates Interrupt Control Across Device Queues A PCI function using MSI-X can expose multiple interrupt vectors whose delivery state is controlled independently. Software can mask one MSI-X table entry while other enabled entries remain able to signal interrupts. That property matters for devices with multiple queues because interrupt control can follow the same partitioning as the I/O work instead of collapsing every notification source behind one device-wide interrupt state.

PCIe MSI-X

Tech 19 Sep 2026 7 min read

MSI-X Lets Device Queues Target Separate CPU Interrupt Paths

MSI-X Lets Device Queues Target Separate CPU Interrupt Paths A multiqueue PCIe device can move data through many queues at once, yet a single interrupt path would funnel completion handling back through one signal. MSI-X removes that device-wide bottleneck from the interrupt interface. Each allocated MSI-X entry represents an independently configurable message-signaled interrupt, so a driver can associate different queues or event classes with different Linux IRQs and CPU affinity policies.

PCIe MSI-X

Tech 17 Sep 2026 6 min read

NIC Interrupt Coalescing Trades CPU Overhead for Packet Latency

A network interface can receive packets faster than a CPU should service one hardware interrupt per packet. Interrupt coalescing addresses that mismatch by allowing the adapter to group completion notifications and interrupt the CPU less often. The tradeoff is explicit. Fewer interrupts reduce interrupt handling and scheduling pressure, but a packet may wait longer before software is told that receive work is ready. The best setting depends on packet rate, latency targets, CPU capacity, and the adapter’s coalescing controls.

Networking NIC