NVMe

Tech / 22 Sep 2026 / 7 min read

NVMe Completion Queue Phase Tags Mark Reused Entries

An NVMe completion queue is a fixed-size circular array in host memory. The controller writes completion queue entries as commands finish, while host software consumes those entries and advances the queue head. Eventually both sides return to slots that already contain data from an earlier circuit of the ring. Reusing memory creates a small but important ambiguity. A slot can contain a perfectly formed completion entry even when the controller has not written a new completion there yet. Clearing every consumed entry would add memory traffic and still require careful coordination between the host and controller.

Storage NVMe

Tech / 22 Sep 2026 / 6 min read

NVMe Completion Queue Phase Tags Distinguish New Entries After Ring Wrap

An NVMe completion queue is a circular memory structure shared by a controller and host software. The controller posts completion queue entries after commands finish, while the host consumes those entries and advances its queue head. Once either side reaches the final slot, its index wraps to slot zero. That wrap creates a small but important state problem. Queue memory still contains bytes from earlier completions. Reading a nonzero entry at the current head is not enough to prove that the controller has posted a fresh completion there. NVMe solves this with a one-bit Phase Tag carried in every completion queue entry.

NVMe Storage

Tech / 17 Sep 2026 / 9 min read

NVMe Queue Pairs Separate Command Submission from Completion

NVMe Queue Pairs Separate Command Submission from Completion An NVMe solid-state drive does not need the CPU to hand each storage command directly to a device register and then wait for that command to finish. Instead, NVMe places command and completion records in queues held in host memory. The controller reads pending commands from submission queues and writes results to associated completion queues. That arrangement matches fast PCIe storage well. Modern SSD controllers can process many operations at once across flash channels, internal dies, and controller pipelines. A queue model lets software keep that parallel hardware busy while avoiding a long series of synchronous command handoffs.

Storage NVMe

Tech / 16 Sep 2026 / 3 min read

NVMe Doorbell Registers Notify Controllers of Queue Progress

NVMe Doorbell Registers Notify Controllers of Queue Progress NVMe places submission and completion queues in host memory, but a controller still needs a signal when software adds commands or consumes completion entries. Doorbell registers provide that signal. Host software writes queue pointer values to memory-mapped controller registers so the device can track progress without scanning host memory continuously. The mechanism separates queue storage from queue notification. Commands and completion entries live in DMA-accessible memory, while small register writes tell the controller which portion of each queue has changed.

Tech NVMe

Tech / 15 Sep 2026 / 6 min read

SSD TRIM Marks Discarded Data for Flash Reuse

Deleting a file changes filesystem metadata, but that action does not automatically tell a solid-state drive which flash pages no longer contain useful data. From the drive’s point of view, previously written logical block addresses can remain valid until the host explicitly replaces them or marks them as discarded. TRIM closes that information gap. The operating system can notify the storage device that selected logical blocks no longer need their old contents. The SSD may then treat the associated data as disposable during its internal space-management work.

Storage SSD

Tech / 15 Sep 2026 / 7 min read

NVMe Queues Let Storage Handle Many Commands in Parallel

NVMe storage does not send every read or write through one shared command line. The protocol is built around queue pairs: software places commands into a submission queue, and the controller reports finished work through a corresponding completion queue. That structure matters most when several processor cores and application threads are generating storage work at the same time. Multiple queues can distribute command handling across cores, reduce contention around a single software path, and keep a fast solid-state drive supplied with enough outstanding work.

Storage NVMe

Tech / 14 Sep 2026 / 4 min read

NVMe APST Moves Idle SSDs Into Lower Power States

An NVMe SSD can support several power states rather than operating at one fixed power level. Active states favor quick access and throughput, while deeper idle states can reduce energy use at the cost of extra time needed to return to full activity. Autonomous Power State Transition, commonly shortened to APST, lets the host configure automatic movement into selected lower-power states after defined idle periods. Once configured, the controller can perform those transitions without a separate host command for every idle event.

NVMe SSD