Tech

Tech / 19 Sep 2026 / 7 min read

Reduce Voice Recording Noise with FFmpeg Without Destroying Speech

A noisy voice recording is not one problem. Low-frequency handling noise, steady microphone hiss, fan noise, electrical hum, room reverberation, clipping, and codec artifacts have different causes, so a single aggressive denoiser rarely fixes all of them cleanly. FFmpeg provides several useful building blocks for offline cleanup. A practical chain often starts by decoding the source, removing frequencies that clearly do not belong to the wanted signal, applying moderate broadband denoising, and writing the result to an uncompressed WAV file for further processing. The important part is restraint: noise reduction that is too strong can replace background noise with metallic, watery, or gated speech artifacts.

Audio FFmpeg

Tech / 19 Sep 2026 / 7 min read

Reading ESP32 I2S Pin Definitions: MCLK, BCLK, WS, DIN, and DOUT

An ESP32 audio configuration can look deceptively similar to ordinary GPIO setup: const uint8_t I2S_MCLK = 0; const uint8_t I2S_SCK = 5; const uint8_t I2S_WS = 25; const uint8_t I2S_SDOUT = 26; const uint8_t I2S_SDIN = 35; These constants do not define five interchangeable audio wires. Each represents a different part of the I2S timing and data path. A speaker amplifier can remain completely silent even when every GPIO is electrically connected if BCLK and WS are missing, the data direction is reversed, or the frame format does not match the receiving device.

ESP32 I2S

Tech / 19 Sep 2026 / 7 min read

Raw IR Capture and Replay on ESP32 Depends on Timing, Frame Boundaries, and Carrier Frequency

An infrared receiver does not hand an ESP32 a universal “button code.” At the electrical boundary, it produces a sequence of detected carrier bursts and gaps. A raw capture represents those intervals as alternating mark and space durations, usually in microseconds. A capture such as: uint16_t rawData[] = { 3570, 1620, 554, 342, 498, 1244, 496, 378, // ... }; is therefore a waveform description. Replaying it successfully depends on preserving four things together: the timing sequence, the correct frame boundary, the modulation carrier used for marks, and enough optical output from the IR LED.

ESP32 Infrared

Tech / 19 Sep 2026 / 5 min read

Power Architecture Inside a Wi-Fi Smart LED Bulb

A mains-powered smart LED bulb has two electrical jobs that should not be collapsed into one. Its LED array needs controlled current at a voltage determined by the LED string, while its Wi-Fi or Bluetooth controller needs a stable low-voltage supply. A simplified architecture is: 220-240 V AC | input protection and rectification | +--> LED power stage --> R / G / B / WW / CW channels | +--> low-voltage supply --> MCU + Wi-Fi/Bluetooth + control logic The exact topology varies between products. The important boundary is the separation between LED power and logic power.

Smart Bulb LED Driver

Tech / 19 Sep 2026 / 7 min read

PCIe Posted Writes Separate CPU Completion from Device Visibility

PCIe Posted Writes Separate CPU Completion from Device Visibility An MMIO store can be complete from the CPU’s point of view while the corresponding write is still moving through the I/O path. PCI and PCIe memory writes are normally posted: the requester does not wait for a completion response for each write. Bridges and interconnect logic can accept the transaction and let the CPU continue before the endpoint has consumed it.

PCIe MMIO

Tech / 19 Sep 2026 / 6 min read

PCIe Posted MMIO Writes Can Outlive the CPU Store That Issued Them

A CPU can retire or complete an MMIO store before the corresponding PCIe Memory Write has reached the target device. The gap exists because PCIe Memory Write requests are posted: the requester sends them without waiting for a completion packet from the completer. That property is useful for throughput, but it creates an important boundary. A software-visible store instruction, an ordering barrier, and device observation of the write are not automatically the same event.

PCIe MMIO

Tech / 19 Sep 2026 / 5 min read

PCIe PASID Lets One Device Carry Multiple Address-Space Contexts

PCIe PASID Lets One Device Carry Multiple Address-Space Contexts A PCIe function normally has a Requester ID derived from its bus, device, and function identity. That identifier tells platform components which function issued a transaction, but it is too coarse when one device serves work from several process address spaces at the same time. Process Address Space ID (PASID) adds another identity field to the transaction path. A PASID can select an address-space context beneath the same device function, allowing the IOMMU to distinguish memory traffic that belongs to different processes without requiring a separate PCIe function for each one.

PCIe PASID

Tech / 19 Sep 2026 / 5 min read

PCIe ATS Moves Address Translation Caching Into the Device

PCIe ATS Moves Address Translation Caching Into the Device An IOMMU can translate DMA addresses on behalf of a device, but that arrangement puts translation machinery in the path of device memory traffic. PCIe Address Translation Services (ATS) adds another option: a capable device can request a translation and retain the result in its own translation cache. Later transactions can carry the translated address instead of requiring the same translation work at the IOMMU for every access.

PCIe ATS

Tech / 19 Sep 2026 / 6 min read

PCIe ASPM Link States Trade Idle Power for Exit Latency

A PCI Express link does not need to keep every transmitter and receiver block fully active when no packets are moving. Active State Power Management, or ASPM, lets a link enter lower-power states during idle periods and return to L0 when traffic resumes. The mechanism sits below application I/O. Software can issue the same storage, network, or device operation regardless of the current link state, but the first transaction after an idle interval can encounter extra delay as the link returns to active operation.

PCIe Power Management

Tech / 19 Sep 2026 / 6 min read

PCIe ACS Controls Whether Peer Traffic Can Bypass the IOMMU

PCIe ACS Controls Whether Peer Traffic Can Bypass the IOMMU An IOMMU can restrict DMA only for transactions that reach its translation and permission checks. PCI Express complicates that boundary because two endpoints under the same hierarchy can exchange peer-to-peer traffic without sending every transaction through the root complex. A switch may be able to route a request directly from one downstream port to another. PCIe Access Control Services (ACS) adds controls for that routing boundary. Depending on the component and supported ACS features, the fabric can validate a request, block selected translated traffic, redirect peer requests or completions upstream, or constrain their egress. The result is not merely a routing preference. ACS can determine whether two devices are separable at the IOMMU boundary.

PCIe ACS

Tech / 19 Sep 2026 / 5 min read

NIC Interrupt Moderation Trades Wakeup Rate for Packet Latency

A network adapter does not need to interrupt a CPU for every received packet or completed transmission. Many NICs can hold interrupt delivery briefly and report several completion events together. This interrupt moderation reduces interrupt traffic and CPU entry overhead, but it can also delay the moment software notices newly completed work. The mechanism sits between packet DMA and the driver’s receive or transmit processing. It changes notification timing; it does not change the packet’s wire format, Ethernet ordering rules, or the basic requirement that the driver eventually process completed descriptors.

Networking Linux

Tech / 19 Sep 2026 / 7 min read

MSI-X Per-Vector Masking Separates Interrupt Control Across Device Queues

MSI-X Per-Vector Masking Separates Interrupt Control Across Device Queues A PCI function using MSI-X can expose multiple interrupt vectors whose delivery state is controlled independently. Software can mask one MSI-X table entry while other enabled entries remain able to signal interrupts. That property matters for devices with multiple queues because interrupt control can follow the same partitioning as the I/O work instead of collapsing every notification source behind one device-wide interrupt state.

PCIe MSI-X

Tech / 19 Sep 2026 / 7 min read

MSI-X Lets Device Queues Target Separate CPU Interrupt Paths

MSI-X Lets Device Queues Target Separate CPU Interrupt Paths A multiqueue PCIe device can move data through many queues at once, yet a single interrupt path would funnel completion handling back through one signal. MSI-X removes that device-wide bottleneck from the interrupt interface. Each allocated MSI-X entry represents an independently configurable message-signaled interrupt, so a driver can associate different queues or event classes with different Linux IRQs and CPU affinity policies.

PCIe MSI-X

Tech / 19 Sep 2026 / 7 min read

Measure Electronic Components with a Digital Multimeter

A digital multimeter combines several electrical measurements in one instrument, but each mode answers a different question. A resistance reading can confirm that a resistor is near its marked value. A diode test can show a plausible forward-voltage drop. A voltage measurement can reveal whether a circuit node is being powered. None of those readings, by itself, proves that an entire circuit is healthy. That distinction matters when testing electronic components. A multimeter is excellent for static and low-frequency checks, especially when the expected electrical condition is known. It is much less informative when the fault depends on waveform shape, switching behavior, noise, timing, or operation under load.

Electronics Multimeter

Tech / 19 Sep 2026 / 6 min read

Layer Height Changes FDM Print Detail, Surface Finish, and Time

In fused deposition modeling (FDM), layer height is the vertical distance assigned to each deposited layer. A model sliced at 0.20 mm is built from nominally 0.20 mm-high layers; changing that value changes how the slicer discretizes the model along the Z axis. That one setting affects several things at once: curved surfaces become more or less visibly stepped, small vertical features may be represented differently, each extrusion line changes shape, and the printer needs a different number of layers to reach the same height.

3D Printing FDM

Tech / 19 Sep 2026 / 6 min read

IOMMU Translation Separates Device DMA Addresses from Physical Memory

A DMA-capable device can issue memory transactions without the CPU copying each payload. On systems with an IOMMU, the address carried by that device transaction does not have to be a host physical address. The IOMMU can translate a device-visible I/O virtual address into a physical page and reject accesses outside the configured mapping. That translation boundary changes both isolation and data movement. Drivers and operating systems can give a device a constrained address space, while the hardware must maintain translation state close enough to the I/O path to avoid turning every DMA request into a page-table walk.

IOMMU DMA

Tech / 19 Sep 2026 / 6 min read

IOMMU IOTLB Invalidation Controls When DMA Remapping Takes Effect

IOMMU IOTLB Invalidation Controls When DMA Remapping Takes Effect Changing an IOMMU page-table entry does not necessarily change the translation used by the next DMA request. An IOMMU can cache address translations in an I/O translation lookaside buffer, commonly called an IOTLB. Software must invalidate affected cached state when a mapping is removed or replaced, then observe the invalidation semantics required by that IOMMU before treating the old translation as retired.

IOMMU DMA

Tech / 19 Sep 2026 / 6 min read

Infrared Sensors Measure Different Physical Effects

An infrared sensor is not a single measurement technology. “IR sensor” can describe a reflective proximity detector, a PIR motion detector, a non-contact temperature sensor, an optical encoder, or an infrared receiver. They all operate with radiation outside the visible spectrum, but the quantity being measured is different. That distinction determines what the sensor can detect, how far it can work, and which environmental conditions can produce false or weak readings.

Infrared Sensors

Tech / 19 Sep 2026 / 6 min read

Hacker and Developer Forums Serve Different Technical Workflows

A developer asking why a PostgreSQL query ignores an index needs a different community from a security researcher comparing exploit mitigations or an Android developer debugging a device-specific kernel problem. They may all be called forums, but their information systems work differently. Some communities optimize for a precise question and a reusable answer. Others preserve long discussions, attach conversation to a software project, publish security research, or rank links that engineers consider worth discussing. Choosing the right venue changes both the quality of the response and how useful the discussion remains months later.

Developer Communities Cybersecurity

Tech / 19 Sep 2026 / 7 min read

GPS Distance and IMU Balance on ESP32 Measure Different Things

A GPS module and an IMU can both feed an ESP32 with numbers that describe motion, but they observe different physical quantities. Treating them as interchangeable sensors creates bad measurements quickly. A GPS receiver estimates geographic position from satellite signals. Two position fixes can be converted into an approximate distance across Earth’s surface. An IMU such as the MPU-6050 measures acceleration and angular rate along its axes. Those measurements can be used to estimate tilt, rotation, and short-term motion.

ESP32 GPS

Tech / 19 Sep 2026 / 7 min read

Gesture-Controlled Air Conditioner with ESP32-S3 Without a Camera

A camera is unnecessary when an air-conditioner controller only needs a small vocabulary of hand motions. The useful signal is not an image of the hand; it is a directional event such as up, down, left, or right. A short-range optical gesture sensor can reduce that input to a few bytes before the ESP32-S3 sees it. That changes the embedded design substantially. There is no camera frame buffer, DVP bus, image preprocessing, or inference model competing with the LCD and infrared transmitter. The ESP32-S3 can spend its resources on the part that actually needs careful handling: keeping the intended AC state synchronized with each gesture and encoding that state into the appliance’s IR protocol.

ESP32-S3 Gesture Sensor

Tech / 19 Sep 2026 / 6 min read

ESP32-S3 HMI Performance Is Mostly a Memory-Bandwidth Problem

An ESP32-S3 can run a touchscreen HMI without a Linux-class processor, but CPU clock alone does not determine whether the interface feels responsive. Once a display uses a large framebuffer, the critical path includes memory capacity, PSRAM bandwidth, DMA traffic, pixel format, pixel clock, and the amount of the screen redrawn for each interaction. The ESP32-S3 combines a dual-core Xtensa LX7 CPU running up to 240 MHz with an LCD/camera peripheral, DMA support, Wi-Fi, Bluetooth LE, and external PSRAM options. That makes it a useful HMI controller, especially when the interface consists of controls, status indicators, charts, configuration pages, and moderate animation.

ESP32-S3 HMI

Tech / 19 Sep 2026 / 5 min read

ESP32 MQTT Sensor State: Publishing DHT22 Temperature and Humidity as One JSON Message

A DHT22 read produces temperature and relative humidity from the same sampling event. Publishing them on separate MQTT topics works, but it also creates two independent message boundaries. A subscriber can receive the new temperature before the matching humidity value arrives. Putting both measurements in one payload preserves the relationship explicitly: {"temperature":25.34,"humidity":60.21} MQTT does not require JSON. The useful property here is that both measurements travel in one publication and can be treated as one sensor-state snapshot.

ESP32 MQTT

Tech / 19 Sep 2026 / 5 min read

ESP-IDF LCD APIs Depend on the Selected SoC Target

An ESP-IDF project can include esp_lcd_panel_io.h successfully and still fail on esp_lcd_i80_bus_config_t or esp_lcd_new_i80_bus(). That combination looks contradictory until the build target is taken into account. esp_lcd is a framework, not a promise that every ESP chip exposes every LCD transport. The selected SoC determines which low-level interfaces are compiled into the project. Panel-controller support, such as ILI9341, is another layer again. That distinction matters when moving code between ESP32 variants.

ESP-IDF ESP32