Tech

Tech / 19 Sep 2026 / 6 min read

Electrolytic Capacitor ESR Turns Ripple Current Into Heat

An aluminum electrolytic capacitor does not behave like an ideal capacitor. Its internal foil, electrolyte, tabs, and contacts add resistance, represented in a simple model as equivalent series resistance, or ESR. When AC ripple current flows through that resistance, the capacitor dissipates real power as heat. For power-supply filtering, this mechanism can matter as much as capacitance and voltage rating. A capacitor may have the expected number of microfarads and still run too hot if its ESR is too high for the ripple current imposed by the circuit.

Electronics Capacitor

Tech / 19 Sep 2026 / 6 min read

Driving an IR LED from an ESP-01: Current, Range, and Transistor Count

An ESP8266 ESP-01 can act as the controller for an infrared AC remote, but the GPIO should be treated as a logic source rather than as the power source for the IR LED. The useful design question is not whether the transmitter has one transistor or three. It is whether the driver can switch the required LED pulse current cleanly while preserving the carrier and protocol timing. That distinction also corrects a common assumption: a three-transistor circuit does not inherently transmit farther than a one-transistor circuit. A correctly sized single transistor or MOSFET can drive an IR LED effectively. Additional transistors only help when they perform a necessary circuit function.

ESP8266 ESP-01

Tech / 19 Sep 2026 / 6 min read

Driving an ILI9341 SPI Display and Touch Controller from ESP32-S3

A 2.4-inch 240 × 320 TFT module built around the ILI9341 is a practical match for an ESP32-S3 because the display controller accepts a serial SPI interface. The module is not necessarily one device: a typical board can contain the ILI9341 for pixels, a separate resistive-touch controller, and sometimes a microSD socket. That distinction determines the wiring. The devices may share SPI clock and data lines, while each peripheral keeps its own chip-select signal.

ESP32-S3 ILI9341

Tech / 19 Sep 2026 / 5 min read

Cache-Line False Sharing Moves Coherence Ownership Between CPUs

Cache-Line False Sharing Moves Coherence Ownership Between CPUs Two threads can update different variables without sharing a lock or touching the same bytes and still interfere at the hardware level. If those variables occupy the same cache line, a coherent multiprocessor treats their storage as one coherence unit. Repeated writes from different CPUs can therefore move ownership of that line between caches even though the program considers the variables independent.

CPU Cache

Tech / 19 Sep 2026 / 7 min read

Boost Converter Power Limits on Small Solar Panels

A 5 V solar panel rated for tens or hundreds of milliamps can feed a boost converter, but the converter does not create additional electrical power. It trades current for voltage while losing some energy as heat. That distinction matters with miniature panels. A nominal 5 V panel rated at 60 mA has only about 0.30 W available at its rated operating point. Raising its output to 9 V is electrically possible only if the load accepts a much smaller current and the panel remains near a useful operating voltage.

Solar Panel Boost Converter

Tech / 19 Sep 2026 / 5 min read

Arduino-IRremote Raw Output: Converting Receive Timings into sendRaw() Data

Arduino-IRremote separates the representation used while receiving an infrared frame from the representation consumed by sendRaw(). The receiver records sampled durations, tracks the gap before the frame separately, and can compensate timing distortion introduced by a demodulating IR receiver. A transmitter, by contrast, expects an array that starts with the first mark and alternates mark and space durations. That boundary matters for AC remotes because their frames can be long and are frequently replayed as RAW data when no protocol-specific encoder is available.

Arduino Infrared

Tech / 19 Sep 2026 / 6 min read

An SPI microSD Slot Does Not Make an 8-Bit TFT Shield an SPI Display

A 2.8-inch Arduino-style TFT shield can place an LCD and a microSD socket on the same PCB while giving them completely different electrical interfaces. The pin labels are the quickest way to tell them apart. On the shield shown here, the LCD side exposes DB0 through DB7 together with LCD_WR, LCD_RD, LCD_RS, LCD_CS, and LCD_RST. Those are the signals of an 8-bit 8080-style parallel display interface. The labels SD_MOSI, SD_MISO, SD_SCK, and SD_SS belong to the microSD socket.

ESP32-C6 TFT LCD

Tech / 17 Sep 2026 / 6 min read

Write Combining Merges Adjacent Stores Before Memory Traffic

Some memory regions are written far more often than they are read. Frame buffers, device apertures, and streaming output areas are common examples. Sending every small CPU store as a separate memory transaction can waste bus bandwidth and transaction overhead. Write combining gives the processor a temporary place to collect compatible stores. Several writes targeting nearby addresses can be merged into a larger transaction before they leave the CPU. The technique favors sustained write throughput, but it changes the timing and ordering properties that software can safely assume.

CPU Memory

Tech / 17 Sep 2026 / 7 min read

PCIe ASPM Trades Link Wake Latency for Idle Power

A PCI Express link does not need to remain at full active power while no packets are moving. Active State Power Management, commonly called ASPM, lets compatible link partners enter lower-power link states during idle periods and return to active operation when traffic resumes. The tradeoff is direct: deeper idle states can save more energy, but leaving them takes time. A system therefore balances link power against the latency added to the next transfer.

PCIe ASPM

Tech / 17 Sep 2026 / 9 min read

NVMe Queue Pairs Separate Command Submission from Completion

NVMe Queue Pairs Separate Command Submission from Completion An NVMe solid-state drive does not need the CPU to hand each storage command directly to a device register and then wait for that command to finish. Instead, NVMe places command and completion records in queues held in host memory. The controller reads pending commands from submission queues and writes results to associated completion queues. That arrangement matches fast PCIe storage well. Modern SSD controllers can process many operations at once across flash channels, internal dies, and controller pipelines. A queue model lets software keep that parallel hardware busy while avoiding a long series of synchronous command handoffs.

Storage NVMe

Tech / 17 Sep 2026 / 6 min read

NUMA Makes Memory Location Part of Access Cost

NUMA Makes Memory Location Part of Access Cost A large multiprocessor server can expose one physical address space while giving different processors different paths to that memory. A load from a page attached to the processor running a thread can take a shorter route than a load from memory attached to another processor package or NUMA node. This arrangement is called non-uniform memory access, or NUMA. It lets systems scale memory capacity and bandwidth across multiple processor sockets or chiplet groups without forcing every memory request through one centralized controller.

CPU Memory

Tech / 17 Sep 2026 / 6 min read

NIC Interrupt Coalescing Trades CPU Overhead for Packet Latency

A network interface can receive packets faster than a CPU should service one hardware interrupt per packet. Interrupt coalescing addresses that mismatch by allowing the adapter to group completion notifications and interrupt the CPU less often. The tradeoff is explicit. Fewer interrupts reduce interrupt handling and scheduling pressure, but a packet may wait longer before software is told that receive work is ready. The best setting depends on packet rate, latency targets, CPU capacity, and the adapter’s coalescing controls.

Networking NIC

Tech / 17 Sep 2026 / 6 min read

Memory Fences Constrain Cross-Core Memory Ordering

Memory Fences Constrain Cross-Core Memory Ordering A processor can execute memory operations with more freedom than source-code order suggests. Loads may begin early, stores may wait in buffers, cache-coherence traffic may complete at different times, and independent operations can overlap. These techniques improve throughput, but concurrent software needs precise rules for publishing and observing shared state. A memory fence places an ordering constraint around selected memory operations. It does not normally flush every cache, serialize the entire processor, or make all cores execute one instruction stream. Its role is narrower: it restricts which memory-order outcomes are permitted across a defined boundary.

CPU Concurrency

Tech / 17 Sep 2026 / 7 min read

IOMMU Remaps Device DMA Addresses for Memory Isolation

Direct memory access lets a device move data between itself and system memory without making the CPU copy every byte. Network adapters, storage controllers, GPUs, and other high-throughput devices rely on DMA to keep data moving efficiently. That capability also creates a protection problem. A device that can issue unrestricted memory transactions could read or overwrite physical pages belonging to the kernel, another process, or another virtual machine. An input-output memory management unit, commonly called an IOMMU, places address translation and access control between DMA-capable devices and physical memory.

IOMMU DMA

Tech / 16 Sep 2026 / 5 min read

USB Selective Suspend Reduces Power for Idle Devices

USB does not require every attached device to remain fully active whenever the computer is running. A host can suspend an idle USB device while other devices continue transferring data. This behavior reduces unnecessary power use, especially on portable systems with several peripherals. The useful distinction is scope: selective suspend targets an idle device or interface rather than treating the entire USB controller as one power unit. Suspend applies to idle USB activity A USB host schedules transfers. When a device has no useful work pending, keeping all of its circuitry active can waste energy.

USB Power Management

Tech / 16 Sep 2026 / 7 min read

TLB Caches Recent Virtual Address Translations

Modern processors commonly execute programs in virtual address spaces. A load or store can begin with a virtual address while the memory system ultimately needs a physical location and access permissions. Page tables hold the mapping information, but consulting their hierarchy for every memory reference would add substantial work. A translation lookaside buffer, or TLB, keeps recently used address translations near the processor. A TLB hit supplies cached mapping information without a full page-table walk. A TLB miss triggers additional translation work even when the requested application data is already present in a CPU cache.

CPU Memory

Tech / 16 Sep 2026 / 6 min read

TCP Window Scaling Expands the Receive Window for Fast Long Paths

TCP flow control limits how much data a sender may have outstanding according to the receiving endpoint’s available buffer space. The receiver advertises that limit in the TCP Window field so the sender does not deliver data faster than the receiving stack can accept it. The Window field in the TCP header is 16 bits wide. Without an extension, its largest value is 65,535 bytes. That ceiling can be too small on a path that carries data quickly but has a substantial round-trip time.

Networking TCP

Tech / 16 Sep 2026 / 6 min read

TCP TIME-WAIT Preserves Closed Connection State

A TCP endpoint can finish an application’s close operation while the protocol still retains state for that connection. After an active close completes its FIN exchange, the endpoint normally enters TIME-WAIT instead of discarding the connection record immediately. That retained state has two jobs. It leaves the endpoint able to acknowledge a retransmitted final FIN, and it separates a closed connection from a later incarnation that could use the same local and remote addresses and ports.

TCP Networking

Tech / 16 Sep 2026 / 6 min read

TCP Keepalive Probes Test Idle Connections

A TCP connection can remain established while carrying no application data. That is valid behavior: an open connection does not need a continuous stream of packets to remain a TCP connection. Silence creates a practical problem when one endpoint disappears without completing the normal close sequence. A machine can lose power, a network path can fail, or state in an intermediate device can vanish. If the surviving endpoint has no data to send, ordinary retransmission logic has nothing to act on.

TCP Networking

Tech / 16 Sep 2026 / 5 min read

SSD TRIM Marks Unused Data for Controller Reclamation

Deleting a file changes filesystem metadata, but an SSD does not automatically know that every flash page formerly associated with the file can be treated as disposable. From the drive’s point of view, previously written logical block addresses can remain valid until the host explicitly indicates otherwise or overwrites them. TRIM provides that indication for ATA storage. Comparable deallocation commands exist in other storage protocols. The host identifies logical block ranges whose previous contents no longer need to be preserved, and the SSD can use that information when managing flash internally.

Storage SSD

Tech / 16 Sep 2026 / 5 min read

SSD Garbage Collection Amplifies Host Writes

An SSD can write substantially more data to NAND than the host sends to the device. The extra traffic appears when the controller must relocate still-valid pages before reclaiming flash blocks that contain invalid data. This internal movement is write amplification. It is a consequence of the mismatch between fine-grained logical updates and NAND erase constraints, not an extra write issued by the application. NAND pages cannot be overwritten in place NAND flash is programmed in pages but erased in larger erase blocks. A page that already contains programmed data cannot generally receive an arbitrary in-place replacement. The controller writes the new version to another available page and marks the old physical page as stale in its mapping state.

Storage SSD

Tech / 16 Sep 2026 / 7 min read

SATA Native Command Queuing Reorders Storage Requests

A storage request does not always need to finish in the same order that software submitted it. SATA Native Command Queuing, commonly shortened to NCQ, lets a compatible host issue several commands without waiting for each one to complete first. The device can then schedule eligible work in an order suited to its internal operation. The mechanism was especially valuable for hard disk drives, where physical head movement and rotational position can make request order affect service time. Solid-state drives have no moving heads, but multiple outstanding commands can still expose parallel work to the controller and reduce idle gaps.

SATA Storage

Tech / 16 Sep 2026 / 3 min read

Receive Side Scaling Distributes Network Flows Across CPU Queues

Receive Side Scaling Distributes Network Flows Across CPU Queues A fast network adapter can receive packets faster than one processor core can handle them efficiently. Receive Side Scaling, commonly abbreviated RSS, spreads incoming traffic across multiple hardware receive queues. Each queue can be associated with a different processor, allowing packet processing to run in parallel. RSS usually assigns packets by flow rather than distributing every packet independently. This preserves useful ordering properties while still spreading many simultaneous connections across available queues.

Tech Networking

Tech / 16 Sep 2026 / 5 min read

PCIe Relaxed Ordering Lets Transactions Pass Within Ordering Rules

PCIe Relaxed Ordering Lets Transactions Pass Within Ordering Rules PCI Express carries requests and completions through switches, bridges, and endpoint logic that can have several transactions in flight at once. Strict ordering between every packet would make many independent transfers wait behind traffic that has no dependency on them. Relaxed Ordering provides a protocol signal that permits more reordering where the requester can tolerate it. The feature does not remove all ordering constraints. It marks a transaction as eligible for additional movement relative to other traffic, while PCIe ordering rules still define which combinations may pass. Software and device logic must only use the attribute when reordering cannot expose stale state or break a producer-consumer dependency.

Tech PCIe