Tech

Tech / 16 Sep 2026 / 5 min read

PCIe Active State Power Management Trades Idle Power for Exit Latency

A PCI Express link does not need to stay at its fully active electrical state while no traffic is moving. Active State Power Management, commonly shortened to ASPM, lets compatible link partners place the link into lower-power states during idle periods. The practical tradeoff is simple: deeper idle states can save more power, but returning to active operation takes time. That exit delay becomes part of the latency seen when new traffic arrives.

PCIe Power Management

Tech / 16 Sep 2026 / 4 min read

Path MTU Discovery Finds Packet Size Limits

Every network link has a maximum transmission unit, or MTU, that limits the size of an IP packet carried in one link-layer frame. A route can cross links with different limits, so the smallest relevant MTU along that route constrains packet size end to end. Path MTU Discovery, commonly shortened to PMTUD, lets an endpoint find that constraint and adjust packet sizes rather than relying on fragmentation. One route can contain several MTU limits Ethernet commonly uses an IP MTU of 1500 bytes, but tunnels, VPNs, encapsulation, and other link types can reduce the usable size. A packet that fits the sender’s local interface can therefore be too large for a later hop.

Networking IP

Tech / 16 Sep 2026 / 3 min read

NVMe Doorbell Registers Notify Controllers of Queue Progress

NVMe Doorbell Registers Notify Controllers of Queue Progress NVMe places submission and completion queues in host memory, but a controller still needs a signal when software adds commands or consumes completion entries. Doorbell registers provide that signal. Host software writes queue pointer values to memory-mapped controller registers so the device can track progress without scanning host memory continuously. The mechanism separates queue storage from queue notification. Commands and completion entries live in DMA-accessible memory, while small register writes tell the controller which portion of each queue has changed.

Tech NVMe

Tech / 16 Sep 2026 / 5 min read

Network Interrupt Coalescing Batches Packets Before CPU Notification

A network interface can receive packets much faster than a CPU should be interrupted for each individual arrival. At high packet rates, one hardware interrupt per packet would consume substantial processor time in interrupt entry, scheduling, driver work, and return paths. Interrupt coalescing changes that pattern. The adapter waits for a small interval, a packet count, or another implementation-specific threshold before notifying the CPU. Several packet arrivals can then be handled from one notification.

Networking NIC

Tech / 16 Sep 2026 / 5 min read

Network Interrupt Coalescing Batches Packet Notifications

A network interface can receive packets far faster than a processor should handle individual hardware interrupts. If every packet immediately triggered an interrupt, high packet rates could consume substantial CPU time in interrupt handling and context transitions. Interrupt coalescing changes that pattern. The network adapter waits for several packets, a short timer, or another configured threshold before notifying the CPU. One interrupt can then cover multiple received packets. The tradeoff is direct: fewer interrupts reduce per-packet CPU overhead, while waiting to form a batch can add latency.

Networking Ethernet

Tech / 16 Sep 2026 / 5 min read

Nagle Algorithm Batches Small TCP Writes

TCP applications can issue writes much smaller than the network’s maximum segment size. Sending every tiny write as a separate segment can consume disproportionate header and processing overhead. The Nagle algorithm limits that pattern by allowing one small segment to remain in flight while later small writes wait for an acknowledgment or enough queued data to form a larger segment. This behavior reduces streams of tiny TCP segments. It can also add latency when an application expects each small write to leave immediately.

TCP Networking

Tech / 16 Sep 2026 / 7 min read

Jumbo Frames Raise Payload Efficiency and MTU Risk

Ethernet networks commonly use an IP maximum transmission unit of 1500 bytes, but many switches, network adapters, and operating systems also support larger frames often called jumbo frames. A larger MTU lets each packet carry more application data before another set of packet headers and per-packet processing is required. That can reduce packet rate for a given throughput. The benefit is most relevant when hosts move large volumes of data and the full path supports the selected frame size.

Networking Ethernet

Tech / 16 Sep 2026 / 5 min read

fsync on a File Does Not Persist Its Directory Entry

A successful fsync() on a regular file does not, by itself, guarantee that the directory entry naming that file has reached persistent storage. Linux documents this boundary explicitly: file synchronization covers the file’s data and associated metadata, while persistence of the containing directory entry requires an fsync() on a file descriptor for that directory. This distinction matters when software creates a new file or atomically replaces an existing pathname. File contents and pathname metadata are separate pieces of filesystem state, and a crash can test the durability boundary between them.

Linux Filesystem

Tech / 16 Sep 2026 / 6 min read

Ethernet Pause Frames Temporarily Stop Link Transmission

Ethernet links can move frames faster than a receiving device can process or forward them. When that mismatch lasts long enough, receive buffers fill and frames may be dropped. IEEE 802.3x flow control provides a link-level response for full-duplex Ethernet. A device can send a MAC Control PAUSE frame that asks its directly connected peer to stop transmitting ordinary data frames for a specified interval. The pause is temporary, local to that link, and different from congestion control performed by higher-layer protocols.

Networking Ethernet

Tech / 16 Sep 2026 / 6 min read

DRAM Refresh Restores Charge Before Bits Fade

Dynamic random-access memory stores data in cells whose electrical state does not remain stable indefinitely. Charge leaks from a cell over time, even when software performs no reads or writes. A memory system therefore has to refresh DRAM periodically to preserve stored bits. Refresh is a maintenance operation rather than a request from an application. The memory controller and DRAM device coordinate it alongside ordinary reads and writes. During parts of that work, some memory resources cannot serve normal requests.

Memory DRAM

Tech / 16 Sep 2026 / 5 min read

DNS Negative Caching Temporarily Stores Name Errors

A DNS cache does not store only successful answers. Recursive resolvers can also retain authoritative responses that say a requested name or record does not exist. This behavior is called negative caching. Negative caching reduces repeated work. If many clients ask for the same absent name, a resolver can answer from its cache instead of sending the same query through the DNS hierarchy each time. The trade-off is temporal. If an administrator adds the missing record while a negative answer is still cached, some clients can continue receiving the cached error until its negative cache lifetime expires.

DNS Networking

Tech / 16 Sep 2026 / 7 min read

CPU Thermal Throttling Reduces Clock Speed at Temperature Limits

A processor can run at a high clock rate only while electrical, power, and temperature limits permit it. Heavy work raises transistor switching activity, which raises power consumption and heat output. If cooling cannot remove that heat quickly enough, the processor approaches a thermal limit. Modern CPUs respond automatically. Control logic reduces performance states so the chip generates less heat. This behavior is commonly called thermal throttling. Thermal throttling is not the same as a processor simply running below its advertised maximum frequency. Boost algorithms already vary clock speed according to workload, active core count, current, power, and temperature. Thermal throttling refers specifically to temperature becoming a limiting condition.

CPU Thermal Management

Tech / 16 Sep 2026 / 6 min read

CPU Store Buffers Decouple Retirement from Cache Writes

A processor does not need every store instruction to finish its cache update before later instructions make progress. Modern cores commonly place completed stores into a store buffer, allowing the instruction to retire while the memory subsystem handles the write afterward. This separation improves throughput because cache ownership, coherence traffic, and other memory activity can take longer than the execution pipeline can afford to wait. The buffer acts as a queue between architectural execution and the cache hierarchy.

CPU Memory

Tech / 16 Sep 2026 / 6 min read

CPU Cache Associativity Limits Where Lines Can Reside

Processor caches keep recently used memory close to execution cores, but cache capacity alone does not determine which data can remain resident. Most general-purpose CPU caches divide storage into sets and give each set a fixed number of slots, commonly called ways. A memory block maps to a particular set. It can occupy any way inside that set, but it cannot move into an unrelated set merely because that other set has free space. This placement rule makes hardware lookup practical and fast, while creating a distinct source of misses when too many active blocks compete for the same set.

CPU Cache

Tech / 16 Sep 2026 / 6 min read

Battery Power Path Prioritizes System Load Before Charging

Plugging a battery-powered device into an adapter does not always mean that adapter current flows straight into the battery first. Many portable designs use a power-path circuit that manages external input, the system load, and the battery as related but distinct power flows. This arrangement lets the device operate while the battery charges. More importantly, it gives the active system priority when the adapter cannot supply both the requested system power and the full programmed charge current.

Battery Charging

Tech / 15 Sep 2026 / 6 min read

USB Selective Suspend Cuts Power Use on Idle Devices

USB devices can remain physically connected while doing no useful work for long periods. Keeping every idle function fully active wastes energy, especially on battery-powered computers with several integrated or external USB devices. Selective suspend gives host software a finer control point. An idle USB function can enter a suspended state while unrelated functions continue operating. When activity is needed again, the host resumes the suspended function and normal transfers continue.

USB Power Management

Tech / 15 Sep 2026 / 5 min read

USB Power Delivery PPS Adjusts Charging Voltage

USB-C chargers can advertise several fixed voltage profiles, but some charging systems benefit from finer control. USB Power Delivery includes Programmable Power Supply, commonly shortened to PPS, which lets a compatible sink request output within an advertised programmable range. That changes where part of the voltage regulation can occur. Instead of receiving one fixed supply level for an extended period and converting all of it inside the device, a phone or other sink can ask the charger to move its output closer to the voltage needed by the device’s charging circuitry.

USB-C Charging

Tech / 15 Sep 2026 / 5 min read

Thermal Throttling Changes Sustained Processor Speed

A processor can finish a short burst of work at a high clock rate and then settle at a lower rate during a long workload. The change does not necessarily indicate a fault. Modern processors operate inside several limits, and temperature is one of the conditions that can reduce the frequency available over time. Thermal throttling is a control response that keeps a processor within permitted operating conditions. It becomes visible when heat generation exceeds what the cooling system can remove while the workload continues. The resulting clock behavior makes peak specifications a poor substitute for sustained performance measurements.

Processors Thermal Throttling

Tech / 15 Sep 2026 / 7 min read

TCP Window Scaling Expands Receive Capacity

A TCP connection can have plenty of bandwidth available and still transfer data below the path’s capacity. One limit can come from flow control: the receiver tells the sender how much additional data it is prepared to accept, and the sender must respect that boundary. The original TCP header allocates 16 bits to the advertised receive window. That field can represent at most 65,535 bytes directly. TCP window scaling extends its effective range by negotiating a multiplier during connection setup, making much larger receive windows possible without changing the size of the header field.

TCP Networking

Tech / 15 Sep 2026 / 5 min read

TCP Nagle Algorithm Batches Small Writes

Applications can hand TCP data in pieces much smaller than the network’s practical segment size. A terminal session, control protocol, or interactive service might produce only a few bytes at a time. Sending every tiny write immediately can create a stream of packets whose headers are much larger than their payloads. The Nagle algorithm reduces that pattern by limiting how aggressively a TCP sender emits new small segments while earlier data is still awaiting acknowledgment.

TCP Networking

Tech / 15 Sep 2026 / 7 min read

TCP Delayed ACK Reduces Acknowledgment Traffic

TCP Delayed ACK Reduces Acknowledgment Traffic TCP acknowledgments provide essential feedback, but sending a separate ACK for every incoming data segment is not always necessary. A receiver can briefly defer an acknowledgment so that one ACK covers more than one segment. This behavior is known as delayed acknowledgment, or delayed ACK. The mechanism reduces packet processing and reverse-path traffic during steady data transfer. It also introduces a timing tradeoff: if another segment does not arrive soon enough, the receiver eventually has to send the pending ACK on its own.

TCP Networking

Tech / 15 Sep 2026 / 5 min read

SSD Write Cache and Sustained Transfer Speed

An SSD can copy the first part of a large file at high speed, then settle at a much lower rate even though nothing else appears to have changed. That drop can be normal. Many consumer SSDs use part of their NAND as a fast write cache, allowing short bursts to finish before the drive has to sustain writes in its denser storage mode. This behavior makes a single peak transfer number a poor description of every write workload. Cache size, free space, NAND type, controller policy, temperature, and the amount of data already waiting inside the drive can all affect the speed seen during a long transfer.

SSD Storage

Tech / 15 Sep 2026 / 6 min read

SSD TRIM Marks Discarded Data for Flash Reuse

Deleting a file changes filesystem metadata, but that action does not automatically tell a solid-state drive which flash pages no longer contain useful data. From the drive’s point of view, previously written logical block addresses can remain valid until the host explicitly replaces them or marks them as discarded. TRIM closes that information gap. The operating system can notify the storage device that selected logical blocks no longer need their old contents. The SSD may then treat the associated data as disposable during its internal space-management work.

Storage SSD

Tech / 15 Sep 2026 / 7 min read

QUIC Connection IDs Keep Sessions Across Address Changes

A network connection is often associated with addresses and ports. That works well while both endpoints keep the same network attachment, but mobile devices regularly move between Wi-Fi and cellular service, and NAT devices can replace an external UDP port while an application is still active. QUIC provides another identifier for the transport connection: the connection ID. A non-zero-length connection ID lets an endpoint associate incoming QUIC packets with existing connection state even when the packet arrives from a different IP address or UDP port.

QUIC Networking